NXP Semiconductors MPC5606S - Page 265

Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 263
Figure 9-27. MCB mode A1 register update in up counter mode
Figure 9-28 shows the A1 register update in up/down counter mode. Note that A2 can be written at any
time within cycle n in order to be used in cycle n + 1. Thus, A1 receives this new value at the next cycle
boundary. Note that the update disable bits OU[n] of the EMIOSOUDIS register can be used to disable
update of the A1 register.
Figure 9-28. MCB mode A1 register update in up/down counter mode
9.5.1.1.5 Output Pulse Width and Frequency Modulation Buffered (OPWFMB) mode
This mode (MODE[0:6]=10110b0) provides waveforms with variable duty cycle and frequency. The
internal channel counter is automatically selected as the time base when this mode is selected. The A1
register indicates the duty cycle and the B1 register the frequency. Both the A1 and B1 registers are
double-buffered to allow smooth signal generation when changing the register values on the fly. 0% and
100% duty cycles are supported.
At OPWFMB mode entry, the output flip-flop is set to the value of the EDPOL bit in the EMIOSC[n]
register.
A1 value
0x000008
0x000008
0x000001
internal counter
0x000004
0x000006
A2 value
0x000008 0x000004
0x000006
0x000002
0x000004
0x000006
write to A2 write to A2
Match A1
Match A1
A1 load signal
8
4
6
Match A1
Counter = A1
Time
cycle n
cycle n+1
cycle n+2
Prescaler ratio = 2
A1 value
0x000006
A2 value
0x000006
0x000005
0x000006
0x000005
A1 load signal
Counter = 2
EMIOSCNT[n]
TIME
write to A2
match A1
match A1
write to A2
0x000001
0x000005
0x000006
0x000006
cycle n
cycle n+1
cycle n+2
Prescaler ratio = 2