Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
264 Freescale Semiconductor
If when entering OPWFMB mode coming out of GPIO mode the internal counter value is not within the
specified range, then the B match will not occur. This will cause the channel internal counter to wrap at
the maximum counter value, which is 0xFFFF for a 16-bit counter. After the counter wrap occurs, it returns
to 0x1 and resumes normal OPWFMB mode operation. Thus in order to avoid the counter wrap condition,
make sure its value is within the 0x1 to B1 register value range when OPWFMB mode is entered.
When a match on comparator A occurs the output register is set to the value of EDPOL. When a match on
comparator B occurs the output register is set to the complement of EDPOL. B1 match also causes the
internal counter to transition to 0x1, thus restarting the counter cycle.
Only values greater than 0x1 are allowed to be written to the B1 register. Loading any other values leads
to unpredictable results.
Figure 9-29 shows the operation of OPWFMB mode regarding output pin transitions and A1/B1 register
match events. Note that the output pin transition occurs when the A1 or B1 match signal is deasserted,
which is indicated by the A1 match negative edge detection signal. If register A1 is set to 0x4, the output
pin transitions four counter periods after the cycle started, plus one system clock cycle. Note that in the
example shown in Figure 9-29, the internal counter prescaler has a ratio of two.
Figure 9-29. OPWFMB A1 and B1 match to Output Register delay
Figure 9-30 shows the generated output signal if A1 is set to 0x0. Since the counter does not reach zero in
this mode, the channel internal logic infers a match as if A1 = 0x1, with the difference that in this case, the
positive edge of the match signal is used to trigger the output pin transition instead of the negative edge
used when A1
= 0x1. Note that the A1 positive edge match signal from cycle n + 1 occurs at the same time
as B1 negative edge match signal from cycle n. This allows using the A1 positive edge match to mask the
B1 negative edge match when they occur at the same time. The result is that no transition occurs on the
output flip-flop and a 0% duty cycle is generated.
8
1
4
match A1 negative edge detection
5
A1 value
0x000004
A1 match
A1 match negative edge detection
output pin
EDPOL = 0
EMIOSCNT
TIME
match B1 negative edge detection
B1 match
B1 match negative edge detection
B1 value
0x000008
system clock
prescaler
Prescaler ratio = 2
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