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NXP Semiconductors MPC5606S - Page 267

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Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 265
Figure 9-30. OPWFMB mode with A1 = 0 (0% duty cycle)
Figure 9-31 describes the timing for loading the A1 and B1 registers. The A1 and B1 loads use the same
signal, which is generated at the last system clock period of a counter cycle. Thus, A1 and B1 are updated
with A2 and B2 values, respectively, at the same time that the counter (EMIOSCNT[n]) is loaded with 0x1.
This event is defined as the cycle boundary. The load signal pulse has a duration of one system clock
period. If A2 and B2 are written within cycle n, their values are available at A1 and B1, respectively, at the
first clock of cycle n + 1, and the new values are used for matches at cycle n + 1. The update disable bits
OU[n] of the EMIOSOUDIS register can be used to control the update of these registers, thus allowing
delay of the A1 and B1 register updates for synchronization purposes.
In Figure 9-31 it is assumed that both the channel and global prescalers are set to 0x1 (each divide ratio is
two), meaning that the channel internal counter transitions at every four system clock cycles. FLAGs can
be generated only on B1 matches when MODE[5] is cleared, or on both A1 and B1 matches when
MODE[5] is set. Since the B1 flag occurs at the cycle boundary, this flag can be used to indicate that A2
or B2 data written on cycle n were loaded to A1 or B1, respectively, thus generating matches in cycle n + 1.
Note that the FLAG has a synchronous operation, meaning that it is asserted one system clock cycle after
the FLAG set event.
1
4
match A1 negative edge detection
5
A1 value
0x000004
A1 match
A1 match negative edge detection
output pin
EDPOL = 0
EMIOSCNT
TIME
match B1 negative edge detection
B1 match
B1 match negative edge detection
B1 value
0x000008
system clock
prescaler
A2 value
0x000000
write to A2
0x000000
A1 match positive edge detection
match A1 positive edge detection
no transition at this point
1
cycle n
cycle n+1
Prescaler ratio = 2

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