Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
266 Freescale Semiconductor
Figure 9-31. OPWFMB A1 and B1 Register update and flags
Figure 9-32 shows the operation of the Output Disable feature in OPWFMB mode. The output disable
forces the channel output flip-flop to the value of the EDPOL bit. This functionality targets applications
that use active high signals and a high-to-low transition at A1 match. In this case, EDPOL should be set to
0. Note that both the channel and global prescalers are set to 0x0 (each divide ratio is one), meaning that
the channel internal counter transitions at every system clock cycle.
EDPOL = 0
cycle n cycle n+1
cycle n+2
A1 value
1
B1 value
B2 value
0x8
0x2
0x6
0x8
0x1
internal counter
0x4
0x6
MODE
[6]
= 1
A2 value
1
0x2
0x4
0x6
0x2
0x4
0x6
0x8
0x6
Output pin
write to B2
write to A2
write to A2
Match A1
Match A1 Match B1
Match B1
Match B1
A1/B1 load signal
due to B1 match cycle n-1
FLAG set event
FLAG pin/register
Prescaler ratio = 4
FLAG clear
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