Configurable Enhanced Modular IO Subsystem (eMIOS200)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 267
Figure 9-32. OPWFMB mode with active output disable
Note that the output disable has a synchronous operation, meaning that the assertion of the Output Disable
input pin causes the channel output flip-flop to transition to EDPOL at the next system clock cycle. If the
Output Disable input is deasserted, the output pin transition occurs at the next A1 or B1 match.
In Figure 9-32 it is assumed that the Output Disable input is enabled and selected for the channel. See
Section 9.4.2.8, eMIOS200 UC Control Register (EMIOSC[n]), for a detailed description of the ODIS and
ODISSL bits, which respectively control enablement and selection of the Output Disable inputs.
The FORCMA and FORCMB bits allow the software to force the output flip-flop to the level
corresponding to a match on comparators A or B, respectively. Similarly, a B1 match on FORCMB sets
the internal counter to 0x1. The FLAG bit is not set by the FORCMA or FORCMB bits being asserted.
Figure 9-33 shows the generation of 100% and 0% duty cycle signals. It is assumed that EDPOL = 0 and
the resultant prescaler value is 1. Initially, A1 = 0x8 and B1 = 0x8. In this case, B1 match has precedence
over A1 match; thus the output flip-flop is set to the complement of the EDPOL bit. This cycle corresponds
to a 100% duty cycle signal. The same output signal can be generated for any A1 value greater than or
equal to B1.
EDPOL = 0
cycle n cycle n +1
cycle n +2
A1 value
B1 value
B2 value
0x000008
0x000002
0x000006
0x000008
0x000001
internal counter
0x000004
0x000006
MODE[6] = 1
A2 value
0x000002
0x000004
0x000006
0x000002
0x000004
0x000006
0x000008
0x000006
Output pin
write to B2
write to A2
write to A2
Match A1
Match A1 Match B1
Match B1
Match B1
due to B1 match cycle n-1
FLAG set event
Output Disable
FLAG pin/register
Prescaler ratio = 1
FLAG set event
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