NXP Semiconductors MPC5606S - Page 302

Deserial Serial Peripheral Interface (DSPI)
MPC5606S Microcontroller Reference Manual, Rev. 7
300 Freescale Semiconductor
Table 11-12 describes the fields in the DSPI status register.
Table 11-12. DSPIx_SR field descriptions
Field Description
0
TCF
TransfeR Complete Flag. Indicates that all bits in a frame have been shifted out. The TCF bit is set
after the last incoming data bit is sampled, but before the t
ASC
delay starts. Refer to
Section 11.8.5.1, Classic SPI transfer format (CPHA = 0) for details. The TCF bit is cleared by
writing 1 to it.
0 Transfer not complete
1 Transfer complete
1
TXRXS
TX and RX Status. Reflects the status of the DSPI. Refer to Section 11.8.2, Start and stop of DSPI
transfers for information on what clears and sets this bit.
0 TX and RX operations are disabled (DSPI is in Stopped state)
1 TX and RX operations are enabled (DSPI is in Running state)
2 Reserved.
3
EOQF
End Of Queue Flag. Indicates that transmission in progress is the last entry in a queue. The EOQF
bit is set when the TX FIFO entry has the EOQ bit set in the command halfword and after the last
incoming data bit is sampled, but before the t
ASC
delay starts. Refer to Section 11.8.5.1, Classic
SPI transfer format (CPHA = 0) for details.
The EOQF bit is cleared by writing 1 to it. When the EOQF bit is set, the TXRXS bit is automatically
cleared.
0 EOQ is not set in the executing command
1 EOQ bit is set in the executing SPI command
Note: EOQF does not function in Slave mode.
4
TFUF
Transmit FIFO Underflow Flag. Indicates that an underflow condition in the TX FIFO has occurred.
The transmit underflow condition is detected only for DSPI modules operating in Slave mode and
SPI configuration. The TFUF bit is set when the TX FIFO of a DSPI operating in SPI Slave mode is
empty, and a transfer is initiated by an external SPI master. The TFUF bit is cleared by writing 1 to it.
0 TX FIFO underflow has not occurred
1 TX FIFO underflow has occurred
5 Reserved.
6
TFFF
Transmit FIFO Fill Flag. Indicates that the TX FIFO can be filled. Provides a method for the DSPI
to request more entries to be added to the TX FIFO. The TFFF bit is set while the TX FIFO is not
full. The TFFF bit can be cleared by writing 1 to it, or an by acknowledgement from the eDMA
controller when the TX FIFO is full.
0 TX FIFO is full
1 TX FIFO is not full
7–11 Reserved.
12
RFOF
Receive FIFO Overflow Flag. Indicates that an overflow condition in the RX FIFO has occurred. The
bit is set when the RX FIFO and shift register are full and a transfer is initiated. The bit is cleared
by writing 1 to it.
0 RX FIFO overflow has not occurred
1 RX FIFO overflow has occurred
13 Reserved.