Display Control Unit (DCU)
MPC5606S Microcontroller Reference Manual, Rev. 7
444 Freescale Semiconductor
Figure 12-87. Location of sync preamble in Narrow mode
Sync Preamble would come continuously for 4 clock cycles as shown in Figure 12-87. It would not depend
upon which byte is coming first in data (MSB or LSB). Sync extraction is done using pdi_datain [7:0].
Sync Extraction identifies the horizontal and vertical blanking period using H and V field of the XYh data
as mentioned in Table 12-68.
ITU 656 Sync preamble pattern (FFh 00h 00h) has to be masked out in the RGB and YCbCr data. The data
stream must not include FFh 00h 00h as the valid pixel data to avoid malfunction by the validation state
machine.
Horizontal blanking period must be coming during the Vertical blanking period. Gap between 2 Horizontal
blanking should be same during Vertical Blanking period as during line active. All Vertical and horizontal
parameter values are validated against the DCU registers programmed by the user. Polarity of hsync and
vsync are selectable. Horizontal blanking and vertical blanking must be aligned as shown in Figure 12-88.
During blanking period it would check for the 80h 10h 80h 10h sequence. This sequence would be present
both during horizontal (line) blanking and vertical (frame) blanking period.
Framing Bit (F field in XYh) would be ignored during extraction. Extraction is valid for RGB565 and
YCbCr422 muxed mode. ECC error is only detected not corrected. It would be calculated using protection
bits in
Table 12-68
Same as External sync mode, value of front and back porches can be zero but pulse width and TFT screen
parameter cannot be zero.
3
2
1
0
P3
P2
P1
P0
Protection bits (used to detect ECC
errors). It would not be used for bit
correction.
Table 12-68. XYh Value (continued)
Bit Value Description
FF 00 00 XY
pdi_data [7:0]
pdi_clk
16-bit RGB (narrow mode) with internal sync (Representation –1)
Note:
Preamble sequence is independent of data sequence
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