DMA Channel Mux (DMACHMUX)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 455
NOTE
Because of the dynamic nature of the system (for example, DMA channel
priorities, bus arbitration, interrupt service routine lengths, etc.), the number
of clock cycles between a trigger and the actual DMA transfer cannot be
guaranteed.
Figure 13-3. DMA mux triggered channels
The DMA channel triggering capability allows the system to schedule regular DMA transfers, usually on
the transmit side of certain peripherals, without the intervention of the processor. This trigger works by
gating the request from the peripheral to the DMA until a trigger event occurs. This is illustrated in
Figure 13-4.
Figure 13-4. DMA mux channel triggering: normal operation
DMA Channel #0
Trigger #1
Trigger #0
Source #1
Source #2
Source #3
Always #1
DMA Channel #3
Always #4
Trigger #3
Source #63
Peripheral request
Tri gg er
DMA request
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