NXP Semiconductors MPC5606S - Page 504

Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
502 Freescale Semiconductor
Figure 15-33 and Table 15-28 define word 7 of the TCDn structure, the biter and control/status fields.
Table 15-27. TCDn Word 6 (TCDn.dlast_sga) field description
Name Description
dlast_sga[31:00:31] Last destination address adjustment or the memory address for the next transfer
control descriptor to be loaded into this channel (scatter/gather)
if (TCD.e_sg = 0) then
Adjustment value added to the destination address at the completion of the outer major
iteration count.
This value can be applied to “restore” the destination address to the initial value, or
adjust the address to reference the next data structure.
else
This address points to the beginning of a 0-modulo-32 region containing the next
transfer control descriptor to be loaded into this channel. This channel reload is
performed as the major iteration count completes. The scatter/gather address must be
0-modulo-32, else a configuration error is reported.
Address: DMA_Offset + 0x1000 + (32 × n) + 0x1C Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
biter[0:15]
W
Reset — — — — — — — — — — — — — — — —
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
bwc major.linkch[0:5] done active
major.
e_link
e_sg d_req
int_ha
lf
int_m
aj
start
W
Reset — — — — — — — — 0 0 — — — — — 0
Figure 15-33. TCDn Word 7 (TCDn.{biter,control/status}) fields
Table 15-28. TCDn Word 7 (TCDn.{biter, control/status}) field descriptions
Name Description
biter.e_link Enable channel-to-channel linking
on minor loop complete
This is the initial value copied into the citer.e_link field when the major loop is completed. The
citer.e_link field controls channel linking during channel execution.
Note: This bit must be equal to the citer.e_link bit. Otherwise, a configuration error will be
reported.
0 The channel-to-channel linking is disabled.
1 The channel-to-channel linking is enabled.