Enhanced Direct Memory Access (eDMA)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 503
biter[0:5]
or
biter.linkch[0:5]
Beginning “major” iteration count
or
Beginning Link channel number
This is the initial value copied into the citer field or citer.linkch field when the major loop is
completed. The citer fields controls the iteration count and linking during channel execution.
if (TCD.biter.e_link = 0) then
No channel-to-channel linking (or chaining) is performed after the inner “minor” loop is
exhausted. TCD word 5, bits [30:25] are used to form a 15 bit biter field.
else
After the “minor” loop is exhausted, the DMA engine initiates a channel service request at the
channel defined by biter.linkch[5:0] by setting that channel’s TCD.start bit.
The value contained in biter.linkch[5:0] must not exceed the number of implemented channels.
biter[6:14] Beginning “major” iteration count
This is the initial value copied into the citer field or citer.linkch field when the major loop is
completed. The citer fields controls the iteration count and linking during channel execution.
This 9- or 15-bit count represents the beginning major loop count for the channel. As the major
iteration count is exhausted, the contents of the entire 16-bit biter entry is reloaded into the
16-bit citer entry.
When the biter field is initially loaded by software, it must be set to the same value as that
contained in the citer field.
If the channel is configured to execute a single service request, the initial values of biter and
citer should be 0x0001.
bwc[0:1] Bandwidth control
This two-bit field provides a mechanism to effectively throttle the amount of bus bandwidth
consumed by the DMA. In general, as the DMA processes the inner minor loop, it continuously
generates read/write, read/write, ... sequences until the minor count is exhausted. This field
forces the DMA to stall after the completion of each read/write access to control the bus request
bandwidth seen by the platform’s cross-bar arbitration switch. To minimize startup latency,
bandwidth control stalls are suppressed for the first two AHB bus cycles and after the last write
of each minor loop.
The dynamic priority elevation setting elevates the priority of the DMA as seen by the cross-bar
arbitration switch for the executing channel. Dynamic priority elevation is suppressed during the
first two AHB bus cycles.
00 No DMA engine stalls
01 Dynamic priority elevation
10 DMA engine stalls for 4 cycles after each r/w
11 DMA engine stalls for 8 cycles after each r/w
Table 15-28. TCDn Word 7 (TCDn.{biter, control/status}) field descriptions (continued)
Name Description
To Next Page
Loading...
