Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
628 Freescale Semiconductor
4. The fourth pass will scan only bits 127-96 of each page.
5. The fifth pass will scan only the ECC bits (8 + 8) and the single and double ECC errors (2 + 2) of
both Double Words of each page.
The 128 bits of data and the 16 ECC data bits are sampled before the eventual ECC correction, while the
single and double error flags are sampled after the ECC evaluation.
Only data from existing and unlocked locations are captured by the MISR.
The MISR can be seeded to any value by writing the UMISR0–4 registers.
The Array Integrity Self Check consists of the following sequence of events:
1. Set UTE in UT0 by writing the related password in UT0.
2. Select the block(s) to be checked by writing 1s to the appropriate register(s) in LMS or HBS
registers.
Note that Lock and Select are independent. If a block is selected and locked, no Array Integrity
Check will occur.
3. Set eventually UT0.AIS bit for a sequential addressing only.
4. Write a logic 1 to the UT0.AIE bit to start the Array Integrity Check.
5. Wait until the UT0.AID bit goes high.
6. Compare UMISR0-4 content with the expected result.
7. Write a logic 0 to the UT0.AIE bit.
8. If more blocks are to be checked, return to step 2.
It is recommended to leave UT0.AIS at 0 and use the proprietary address sequence that checks the read
path more fully, although this sequence takes more time.
During the execution of the Array Integrity Check operation it is forbidden to modify the content of Block
Select (LMS, HBS) and Lock (LML, SLL, HBL) registers, otherwise the MISR value can vary in an
unpredictable way.
While UT0.AID is low and UT0.AIE is high, the user may clear AIE, resulting in a Array Integrity Check
abort.
UT0.AID must be checked to know when the aborting command has completed.
Example 17-12. Array Integrity check of sectors B0F1 and B0F2
UT0 = 0xF9F99999; /* Set UTE in UT0: Enable User Test */
LMS = 0x00000006; /* Set LSL2-1 in LMS: Select Sectors */
UT0 = 0x80000002; /* Set AIE in UT0: Operation Start */
do /* Loop to wait for AID=1 */
{ tmp = UT0; /* Read UT0 */
} while ( !(tmp & 0x00000001) );
data0 = UMISR0; /* Read UMISR0 content*/
data1 = UMISR1; /* Read UMISR1 content*/
data2 = UMISR2; /* Read UMISR2 content*/
data3 = UMISR3; /* Read UMISR3 content*/
data4 = UMISR4; /* Read UMISR4 content*/
UT0 = 0x00000000; /* Reset UTE and AIE in UT0: Operation End */
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