Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 629
17.3.7.4.2 Margin read
Margin read procedure (either Margin 0 or Margin 1), can be run on unlocked blocks in order to unbalance
the Sense Amplifiers, respect to standard read conditions, so that all the read accesses reduce the margin
vs. 0 (UT0.MRV = 0) or vs. 1 (UT0.MRV = 1). Locked sectors are ignored by MISR calculation and ECC
flagging. The results of the margin reads can be checked comparing checksum value in UMISR0-4.
Since Margin reads are done at voltages that differ than the normal read voltage, lifetime expectancy of
the flash memory macrocell is impacted by the execution of Margin reads. Doing Margin reads repetitively
results in degradation of the flash memory array, and shorten expected lifetime experienced at normal read
levels. For these reasons the Margin read usage is allowed only in Factory, while it is forbidden to use it
inside the User Application. In any case the charge losses detected through the Margin mode cannot be
considered failures of the device and no Failure Analysis will be opened on them.
The Margin Read Setup operation consists of the following sequence of events:
1. Set UTE in UT0 by writing the related password in UT0.
2. Select the block(s) to be checked by writing 1’s to the appropriate register(s) in LMS or HBS
registers.
Note that Lock and Select are independent. If a block is selected and locked, no Array Integrity
Check will occur.
3. Set eventually UT0.AIS bit for a sequential addressing only.
4. Change the value in the UT0.MRE bit from 0 to 1.
5. Select the Margin level: UT0.MRV=0 for 0’s margin, UT0.MRV=1 for 1’s margin.
6. Write a logic 1 to the UT0.AIE bit to start the Margin Read Setup or skip to step 6 to terminate.
7. Wait until the UT0.AID bit goes high.
8. Compare UMISR0-4 content with the expected result.
9. Write a logic 0 to the UT0.AIE, UT0.MRE and UT0.MRV bits.
10. If more blocks are to be checked, return to step 2.
It is recommended to leave UT0.AIS at 1 and use the linear address sequence that takes less time.
During the execution of the Margin mode operation it is forbidden to modify the content of Block Select
(LMS, HBS) and Lock (LML, SLL, HBL) registers, otherwise the MISR value can vary in an
unpredictable way.
The read accesses will be done with the addition of a proper number of Wait States to guarantee the
correctness of the result.
While UT0.AID is low and UT0.AIE is high, the User may clear AIE, resulting in a Array Integrity Check
abort.
UT0.AID must be checked to know when the aborting command has completed.
Example 17-13. Margin Read setup versus 1s
UT0 = 0xF9F99999; /* Set UTE in UT0: Enable User Test */
LMS = 0x00000006; /* Set LSL2-1 in LMS: Select Sectors */
UT0 = 0x80000004; /* Set AIS in UT0: Select Operation */
UT0 = 0x80000024; /* Set MRE in UT0: Select Operation */
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