NXP Semiconductors MPC5606S - Page 119

Safety
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 117
Figure 4-5 showed four registers that can be protected 8-bit wise. In Figure 4-6 registers with 16-bit
protection and in Figure 4-7 registers with 32-bit protection are shown:
Figure 4-6. Change lock settings for 16-bit protected addresses
On the right side of Figure 4-6 it is shown that the data written to SLBRn.SLB[0] is automatically written
to SLBRn.SLB[1] also. This is done as the address reflected by SLBRn.SLB[0] is protected 16-bit wise.
Note that in this case the write enable SLBRn.WE[0] must be set while SLBRn.WE[1] does not matter. As
the enable bits SLBRn.WE[3:2] are cleared the lock bits SLBRn.SLB[3:2] remain unchanged.
In the example on the left side of Figure 4-6 the data written to SLBRn.SLB[0] is mirrored to
SLBRn.SLB[1] and the data written to SLBRn.SLB[2] is mirrored to SLBRn.SLB[3], as for both registers
the write enables are set.
In Figure 4-7 a 32-bit wise protected register is shown. When SLBRn.WE[0] is set the data written to
SLBRn.SLB[0] is automatically written to SLBRn.SLB[3:1] also. Otherwise SLBRn.SLB[3:0] remains
unchanged.
Figure 4-7. Change lock settings for 32-bit protected addresses
Figure 4-8 shows an example that has a mixed protection size configuration:
SLB0 SLB1 SLB2 SLB3
SLBR
update lock bits
1SLBRn.WE[3:0]
to SLB0
write data
to SLB1 to SLB2 to SLB3
X1X
SLB0 SLB1 SLB2 SLB3
SLBR
update lock bits
1SLBRn.WE[3:0]
to SLB0
write data
to SLB1 to SLB2 to SLB3
X00
1
SLB0 SLB1 SLB2 SLB3
SLBRn.WE[3:0]
SLBR.SLB[3:0]
update lock bits
to SLB0
write data
to SLB1 to SLB2 to SLB3
XXX