Revision History
MPC5606S Microcontroller Reference Manual, Rev. 7
1332 Freescale Semiconductor
Flash Memory Added a “Sector” column to the “Flash module sectorization” table.
In the “Flash module sectorization” table, changed the code-flash entries B1F0–3 to
B2F0–3 and the data-flash entries B0F0–3 to B1F0–3.
In the “Program flash memory (Code Flash 0 and Code Flash 1)” section:
• Added a note to the BIU0–2 registers that they are available only on code flash 0.
• In the “Functional description” > “Reset” section, added the text “Reset and power-off
must not be used systematically to terminate a Program or Erase operation”.
• Revised the description of the MCR and UT0.
• In the “Functional description” > “Programming considerations” section, revised the
“Modify Operation” section. (This includes a complete replacement of the “Margin Read”
subsection and deletion of the “Read Reset” subsection.)
• Deleted the “Register map” section.
• Deleted the “Read reset” entry from the “Flash modify operations” table.
In the “Data flash memory” section:
• Revised the “80 KB flash module sectorization” table.
• In the “Functional description” > “Reset” section, added the text “Reset and power-off
must not be used systematically to terminate a Program or Erase operation”.
• Revised the description of the MCR and UT0.
• Revised the NVLML[LLK], NVSLL[SLK], and LMS[LSL] field descriptions.
• Deleted the “Register map” section.
• Deleted the “Read reset” entry from the “Flash modify operations” table
• In the “Functional description” > “Programming considerations” section, revised the
“Modify Operation” section. (This includes a complete replacement of the “Margin Read”
subsection and deletion of the “Read Reset” subsection.)
Changed “Disable Mode” to “Power-Down Mode” and “Sleep Mode” to “Low Power Mode”.
In the “Low Address Space configuration” table, changed the entry for 001 (was reserved,
is “2128 KB”).
In the “Mid Address Space configuration” table, changed the entry for 0 (was “2 x 128KB”,
is “2128 KB or 0 KB”).
Revised the LML[MLK] and LML[LLK] field descriptions.
Revised the HBL[HLK] field description.
Revised the SLL[SMK] field description.
Revised the SLL[SMK] and SLL[SLK] field descriptions.
Revised the LMS[MSL] and LMS[LSL] field descriptions.
Revised the HBS[HSL] field description.
Revised the UT0[AIS] and UT0[AIE] field descriptions.
Revised the UT0 values in the “ECC logic check” example.
Revised the “Bit manipulation: Double Words with the same ECC value” table.
Revised the NVUSR0[WATCHDOG_EN] field description.
Internal Static RAM Revised the “SRAM memory map” table.
In the “General-purpose SRAM” section, changed “plus 16 KB or 40 KB of non-standby
SRAM” to “plus 16 KB or 40 KB of SRAM that may or may not be enabled in standby
mode”.
In the “Low power configuration” section, changed “powered during standby mode” to
“powered by default during standby mode”.
Added the text “Upper RAM is disabled by the MC_PCU” to the “Low power configuration”
table.
Memory Protection
Unit
Added information about MPU region descriptors 8–11.
Added information about MPU region alternate access controls 8–11.
Table C-4. Changes between revisions 3 and 4 (continued)
Chapter Description
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