NXP Semiconductors MPC5606S - Page 645

Flash Memory
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 643
memory banks. Additionally, it includes fields that provide specific information for the two separate AHB
ports (p0 and p1). The register is described below in Figure 17-44 and Table 17-64.
Offset 0x01C Access: Read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
B02_APC B02_WWSC B02_RWSC
B02_
RW
WC
W
Reset 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
B02_
RW
WC
B02_P1_B
CFG
B02_
P1_
DPF
E
B02_
P1_I
PFE
B02_P1_PF
LM
B02_
P1_B
FE
B02_
RW
WC
B0_P0_BC
FG
B02_
P0_
DPF
E
B02_
P0_I
PFE
B02_P0_PF
LM
B02_
P0_B
FE
W
Reset 1 0 0 1 0 0 1 1 1 1 1 0 1 1 0 1
Figure 17-44. PFLASH Configuration Register 0 (PFCR0)
Table 17-64. PFLASH Configuration Register 0 field descriptions
Field Description
B02_APC Bank0+2 Address Pipelining Control. This field is used to control the number of cycles between
flash array access requests. This field must be set to a value appropriate to the operating frequency
of the PFLASH. The required settings are documented in
Table 17-70. Higher operating
frequencies require non-zero settings for this field for proper flash operation. This field is set to
0b00010 by hardware reset.
00000 Accesses may be initiated on consecutive (back-to-back) cycles
00001 Access requests require one additional hold cycle
00010 Access requests require two additional hold cycles
...
11110 Access requests require 30 additional hold cycles
11111 Access requests require 31 additional hold cycles
B02_WWSC Bank0+2 Write Wait State Control. This field is used to control the number of wait-states to be
added to the flash array access time for writes. This field must be set to a value appropriate to the
operating frequency of the PFLASH. The required settings are documented in Tabl e 17-70. Higher
operating frequencies require non-zero settings for this field for proper flash operation. This field is
set to 0b00010 by hardware reset.
00000 No additional wait-states are added
00001 1 additional wait-state is added
00010 2 additional wait-states are added
...
111111 31 additional wait-states are added