Memory Protection Unit (MPU)
MPC5606S Microcontroller Reference Manual, Rev. 7
Freescale Semiconductor 889
24.2.2.4.2 MPU Region Descriptor n, Word 1 (MPU_RGDn.Word1)
The second word of the MPU region descriptor defines the 31-modulo-32 byte end address of the memory
region. Writes to this word clear the region descriptor’s valid bit (see Section 24.2.2.4.4, MPU Region
Descriptor n, Word 3 (MPU_RGDn.Word3) for more information).
24.2.2.4.3 MPU Region Descriptor n, Word 2 (MPU_RGDn.Word2)
The third word of the MPU region descriptor defines the access control rights of the memory region. The
access control privileges are dependent on two broad classifications of bus masters. Bus masters 0-3 are
typically reserved for processor cores and the corresponding access control is a 6-bit field defining
separate privilege rights for user and supervisor mode accesses as well as the optional inclusion of a
process identification field within the definition. Bus masters 4-7 are typically reserved for data movement
engines and their capabilities are limited to separate read and write permissions. For these fields, the bus
master number refers to the logical master number defined as the AHB hmaster[3:0] signal.
For the processor privilege rights, there are three flags associated with this function: {read, write, execute}.
In this context, these flags follow the traditional definition:
• Read (r) permission refers to the ability to access the referenced memory address using an operand
(data) fetch.
Offset MPU_Base + 0x400 + (16*n) + 0x0 (MPU_RGDn.Word0) Access:Read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
SRTADDR
0 0 0 0 0
W
Reset - - - - - - - - - - - - - - - - - - - - - - - - - - - 0 0 0 0 0
Figure 24-5. MPU Region Descriptor, Word 0 Register (MPU_RGDn.Word0)
Table 24-5. MPU_RGDn.Word0 field descriptions
Field Description
0–26
SRTADDR
Start Address. This field defines the most significant bits of the 0-modulo-32 byte start address of the
memory region.
Offset MPU_Base + 0x400 + (16*n) + 0x4 (MPU_RGDn.Word1) Access:Read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
ENDADDR
1 1 1 1 1
W
Reset - - - - - - - - - - - - - - - - - - - - - - - - - - - 1 1 1 1 1
Figure 24-6. MPU Region Descriptor, Word 1 Register (MPU_RGDn.Word1)
Table 24-6. MPU_RGDn.Word1 field descriptions
Field Description
0–26
ENDADDR
End Address. This field defines the most significant bits of the 31-modulo-32 byte end address of the
memory region. There are no hardware checks to verify that ENDADDR SRTADDR; it is software’s
responsibility to properly load these region descriptor fields.
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