NXP Semiconductors MPC5606S - Page 892

Memory Protection Unit (MPU)
MPC5606S Microcontroller Reference Manual, Rev. 7
890 Freescale Semiconductor
•Write (w) permission refers to the ability to update the referenced memory address using a store
(data) instruction.
• Execute (x) permission refers to the ability to read the referenced memory address using an
instruction fetch.
The evaluation logic defines the processor access type based on multiple AHB signals, as hwrite and
hprot[1:0].
For non-processor data movement engines (bus masters 4-7), the evaluation logic simply uses hwrite to
determine if the access is a read or write.
Writes to this word clear the region descriptor’s valid bit (see Section 24.2.2.4.4, MPU Region Descriptor
n, Word 3 (MPU_RGDn.Word3) for more information). Since it is also expected that system software may
adjust only the access controls within a region descriptor (MPU_RGDn.Word2) as different tasks execute,
an alternate programming view of this 32-bit entity is provided. If only the access controls are being
updated, this operation should be performed by writing to MPU_RGDAACn (Alternate Access Control n)
as stores to these locations do not affect the descriptor’s valid bit.
Offset MPU_Base + 0x400 + (16*n) + 0x8 (MPU_RGDn.Word2) Access:Read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R M
7
R
E
M
7
W
E
M
6
R
E
M
6
W
E
M
5
R
E
M
5
W
E
M
4
R
E
M
4
W
E
M
3
P
E
M3S
M
M3UM
r w x
M
2
P
E
M2S
M
M2UM
r w x
M
1
P
E
M1S
M
M1UM
r w x
M
0
P
E
M0S
M
M0UM
r w x
W
Reset - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
Figure 24-7. MPU Region Descriptor, Word 2 Register (MPU_RGDn.Word2)
Table 24-7. MPU_RGDn.Word2 field descriptions
Field Description
0
M7RE
Bus master 7 read enable. If set, this flag allows bus master 7 to perform read operations. If cleared, any
attempted read by bus master 7 terminates with an access error and the read is not performed.
1
M7WE
Bus master 7 write enable. If set, this flag allows bus master 7 to perform write operations. If cleared,
any attempted write by bus master 7 terminates with an access error and the write is not performed.
2
M6RE
Bus master 6 read enable. If set, this flag allows bus master 6 to perform read operations. If cleared, any
attempted read by bus master 6 terminates with an access error and the read is not performed.
3
M6WE
Bus master 6 write enable. If set, this flag allows bus master 6 to perform write operations. If cleared,
any attempted write by bus master 6 terminates with an access error and the write is not performed.
4
M5RE
Bus master 5 read enable. If set, this flag allows bus master 5 to perform read operations. If cleared, any
attempted read by bus master 5 terminates with an access error and the read is not performed.
5
M5WE
Bus master 5 write enable. If set, this flag allows bus master 5 to perform write operations. If cleared,
any attempted write by bus master 5 terminates with an access error and the write is not performed.
6
M4RE
Bus master 4 read enable. If set, this flag allows bus master 4 to perform read operations. If cleared, any
attempted read by bus master 4 terminates with an access error and the read is not performed.
7
M4WE
Bus master 4 write enable. If set, this flag allows bus master 4 to perform write operations. If cleared,
any attempted write by bus master 4 terminates with an access error and the write is not performed.