R&S RTO6 - 18.3.2.1 Hardware CDR setup

Jitter analysis and clock data recovery
R&S
®
RTO6
1116User Manual 1801.6687.02 ─ 05
Hardware CDR is a continuous process, the recovered clock is always synchronized.
HW CDR is the best way to analyze the jitter and eyes of continuous signals, and of
buses that use Spread Spectrum Clocking. The complete data can be used, there is no
synchronization time needed as with SW CDR, and no data must be discarded. Even
short acquisitions are useable with HW CDR. For burst signals, HW CDR can be used
for decoding, but it is inapplicable for eye and jitter measurement.
The recovered clock can be used:
●
As trigger source for the CDR trigger, which is the basis for reliable jitter measure-
ments, see
Chapter 18.3.2.2, "CDR trigger", on page 1118.
●
For the serial pattern trigger, see Chapter 18.3.2.3, "Serial pattern trigger using
CDR", on page 1119.
●
For TIE, unit interval and data rate measurements, see Chapter 18.1.2.3, "Data
measurement settings", on page 1074.
●
Display the generated clock as math waveform, see Chapter 18.3.3, "Displaying
the recovered clock signal", on page 1120.
Jitter measurements and the recovered clock math waveform, which are based on HW
CDR, interpret and display the acquired jitter data. If you change the HW CDR settings,
a new acquisition is required. To acquire jitter data with HW CDR, the trigger type
"CDR" or the trigger type "Serial pattern" with active CDR is required.
18.3.2.1 Hardware CDR setup
Access: "Menu" > "Trigger" > "Setup" tab > "Type = Serial Pattern" > "Hardware CDR"
Source
Selects the channel signal that is used for clock recovery.
Clock data recovery