R&S RTO6 - 13.26.1 The PCIe protocol

Protocol analysis
R&S
®
RTO6
935User Manual 1801.6687.02 ─ 05
● PCIe trigger...........................................................................................................
942
● PCIe Gen 1/2 decode results................................................................................
952
● PCIe Gen 1/2 search.............................................................................................953
13.26.1 The PCIe protocol
The PCIe is a high-speed serial computer expansion bus standard.
The communication between two PCIe devices is performed through logical connec-
tions called links. Each link consists of several lanes. The lanes contain one differential
signaling pair for receiving data and the other for transmitting it.
PCIe logical layers
The PCIe has three logical layers:
●
Transaction layer: assembles and disassembles transaction layer packets (TLPs).
TLP transfer information like read and write and some event types.
●
Data link layer: used for link management and data integrity. Error detection and
correction are also done in this layer. The data link layer produces data link layer
packets (DLLP).
●
Physical layer: includes the circuitry for the interface operation.
PCIe Packet Types
The communication between the layers is done through packets. All packet types that
can be decoded by the R&S RTO6 are listed below.
SCPI name Description Type
MRD32 / MRD64 Memory Read Request for 32 bit/ 64-bit
addresssing packet format
TLP
MRDLK32 / MRDLK64 Memory Read Request-Locked for 32 bit/
64-bit addresssing packet format
TLP
MWR32 / MWR64 Memory Write Request for 32 bit/ 64-bit
addresssing packet format
TLP
IORD I/O Read Request TLP
IOWR I/O Write Request TLP
CFGRD0 / CFGRD1 Configuration Read Type 0/1 TLP
CFGWR0 / CFGWR1 Configuration Write Type 0/1 TLP
TCfgRd / TCfgWr Deprecated TLP Type TLP
MSG Message Request TLP
MSGD Message Request with data payload TLP
CPL Completion without Data TLP
CPLD Completion with Data TLP
PCIe (option R&S RT
O6-K72)