Protocol analysis
R&S
®
RTO6
755User Manual 1801.6687.02 ─ 05
13.17.1 The RFFE protocol
The RFFE interface is specified in the "MIPI
®
Alliance Specification for RF Front-End
Control Interface". The RFFE interface is used by the radio frequency front-end inter-
face chips in most L
TE-Advanced platforms and in smart phones in general. RFFE is a
replacement for existing standards like SPI and I²C that do no meet performance
requirements.
Bus structure
RFFE is a two-wire, serial interface that connects up to 4 master devices (Radio Fre-
quency IC, RFIC) to up to 15 slaves (front-end modules, FEM) on a single RFFE bus.
A slave device has read-write capability
, or it is write only. Only one of the masters is
the active master (bus owner master, BOM), which can initiate command sequences
on the bus.
The interface has two lines: one clock signal (SCLK) controlled by the master, and a
serial bidirectional data signal (SDATA). Furthermore, a VIO supply/reference voltage
from a common source is applied to all components on the bus.
Master
(RFIC)
Slave 1
(FEM 1)
Slave 2
(FEM 2)
External VIO
supply
Slave n
(FEM n)
Figure 13-31: RFFE bus structure with external VIO supply
Command sequences
Protocol messages are called command sequences in RFFE. The standard defines
various command sequences to accomplish read and write access to slaves and to
non-active masters. Command sequences are initiated by the BOM master on the
SDAT
A line.
In general, a command sequence consists of:
●
Sequence start condition (SSC)
RFFE (option R&S R
T
O6-K550)
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