R&S RTO6 - Page 756

Protocol analysis
R&S
®
RTO6
756User Manual 1801.6687.02 ─ 05
Two bits: 1 followed by 0 on SDATA while SCLK is at logic level zero.
●
Command frame
Consist of a 4-bit slave address field (SA), followed by 8 command payload bits
and a single parity bit.
●
Address and/or data frames, depending on the command sequence
A frame consists of 8 data bits or 8 register address bits, followed by a single parity
bit. The number of address and data frames varies depending on the command
sequence type.
●
Bus park cycle (BP)
A BP cycle is sent at the end of a command sequence, and when the device trans-
fers control of SDAT
A to another device.
Between the end of a command sequence and the beginning of a new command
sequence, the bus is in idle condition at least for 10 ns.
The bits are sent MSB first.
SSC
Command payload
8 bits + P
SA
4 bits
[Data frames]
8 bits + P
[Address frames]
8 bits + P
BP
Command frame Address and data frames
Figure 13-32: General structure of a RFFE Write command sequence
SSC
Command payload
8 bits + P
SA
4 bits
[Data frames]
8 bits + P
[Address frames]
8 bits + P
BP
Command frame Address and data frames
BP
Figure 13-33: General structure of a RFFE Read command sequence
Trigger
The R&S RT
O6 uses a hardware-based trigger to trigger on various parts of slave
device messages, to trigger at maximum bus speed and on frame gaps. The data and
clock lines must be connected to the input channels. Triggering on math and reference
waveforms is not possible.
You can trigger on:
●
Start of command sequence (SSC). In addition, you can specify a slave address.
●
End of command sequence). In addition, you can specify a slave address.
●
Various errors, for example, parity and bus park error
●
Read and write command sequences between the BOM and the slaves.
Within a command sequence, you can trigger on specific parts of the message:
– Slave address
– Byte count
– Register address
RFFE (option R&S R
TO6-K550)