R&S RTO6 - Page 2348

Remote control commands
R&S
®
RTO6
2348User Manual 1801.6687.02 ─ 05
V2
PCIe Gen2 (5 Gbit/s)
*RST: V1
BUS<m>:PCIE:LNKW <LinkWidth>
Sets the link width, the number of lanes that are used for the transmission of the data.
Suffix:
<m>
.
1..4
Parameters:
<LinkWidth> X1 | X2 | X4
*RST: X1
BUS<m>:PCIE:LZER:SOURce <SourceL0>
Sets the signal sources for Lane 0.
Suffix:
<m>
.
1..4
Parameters:
<SourceL0> C1W1 | C2W1 | C3W1 | C4W1 | M1 | M2 | M3 | M4 | M5 | M6 |
M7 | M8 |
R1 | R2 | R3 |
R4
*RST: C1W1
BUS<m>:PCIE:LONE:SOURce <SourceL1>
BUS<m>:PCIE:LTWO:SOURce
<SourceL2>
BUS<m>:PCIE:LTHRee:SOURce <SourceL3>
Sets the signal sources for the corresponding logical lane.
Suffix:
<m>
.
1..4
Parameters:
<SourceL3> C1W1 | C2W1 | C3W1 | C4W1 | M1 | M2 | M3 | M4 | M5 | M6 |
M7 | M8 | R1 | R2 | R3 |
R4 | NONE
*RST: LONe: C2W1, LTWo: C3W1, LTHree: C4W1
BUS<m>:PCIE:LZER:THRHigh <ThresholdL0High>
BUS<m>:PCIE:LONE:THRHigh <ThresholdL1High>
BUS<m>:PCIE:L
TWO:THRHigh
<ThresholdL2High>
BUS<m>:PCIE:LTHRee:THRHigh <ThresholdL3High>
Sets the high threshold value for the respective lane.
Suffix:
<m>
.
1..4
Protocols