Infineon TRAVEO T2G - 15.25.7.5 GPIO_PRT_IN

Technical Reference Manual 002-29852 Rev. *B
15.25.7.5 GPIO_PRT_IN
Description:
Port input state register
Address:
0x40310010
Offset:
0x10
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Used to read current pin status for IO pins that have their input buffer enabled (see CFG_IN).
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name IN7 [7:7] IN6 [6:6] IN5 [5:5] IN4 [4:4] IN3 [3:3] IN2 [2:2] IN1 [1:1] IN0 [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:9] FLT_IN
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 IN0 R W 0 IO pin state for pin 0
'0': Low logic level present on pin.
'1': High logic level present on pin.
On reset assertion , IN register will get reset. The Pad
value takes 2 clock cycles to be reflected into IN
Register. It's value then depends on the external pin
value.
1 IN1 R W 0 IO pin state for pin 1
2 IN2 R W 0 IO pin state for pin 2
3 IN3 R W 0 IO pin state for pin 3
4 IN4 R W 0 IO pin state for pin 4
5 IN5 R W 0 IO pin state for pin 5
6 IN6 R W 0 IO pin state for pin 6
7 IN7 R W 0 IO pin state for pin 7
8 FLT_IN R W 0 Reads of this register return the logical state of the
filtered pin as selected in the INTR_CFG.FLT_SEL
register.
1000
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers