Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
DW0_CH_STRUCT60_TR_CMD
0x40288F28 FULL Channel software trigger
9.1.1.62 CH_STRUCT 61
Register Name Address Permission Description
DW0_CH_STRUCT61_CH_CTL
0x40288F40 FULL Channel control
DW0_CH_STRUCT61_CH_STATUS
0x40288F44 FULL Channel status
DW0_CH_STRUCT61_CH_IDX
0x40288F48 FULL Channel current indices
DW0_CH_STRUCT61_CH_CURR_PTR
0x40288F4C FULL Channel current descriptor pointer
DW0_CH_STRUCT61_INTR
0x40288F50 FULL Interrupt
DW0_CH_STRUCT61_INTR_SET
0x40288F54 FULL Interrupt set
DW0_CH_STRUCT61_INTR_MASK
0x40288F58 FULL Interrupt mask
DW0_CH_STRUCT61_INTR_MASKED
0x40288F5C FULL Interrupt masked
DW0_CH_STRUCT61_SRAM_DATA0
0x40288F60 FULL SRAM data 0
DW0_CH_STRUCT61_SRAM_DATA1
0x40288F64 FULL SRAM data 1
DW0_CH_STRUCT61_TR_CMD
0x40288F68 FULL Channel software trigger
9.1.1.63 CH_STRUCT 62
Register Name Address Permission Description
DW0_CH_STRUCT62_CH_CTL
0x40288F80 FULL Channel control
DW0_CH_STRUCT62_CH_STATUS
0x40288F84 FULL Channel status
DW0_CH_STRUCT62_CH_IDX
0x40288F88 FULL Channel current indices
DW0_CH_STRUCT62_CH_CURR_PTR
0x40288F8C FULL Channel current descriptor pointer
DW0_CH_STRUCT62_INTR
0x40288F90 FULL Interrupt
DW0_CH_STRUCT62_INTR_SET
0x40288F94 FULL Interrupt set
DW0_CH_STRUCT62_INTR_MASK
0x40288F98 FULL Interrupt mask
DW0_CH_STRUCT62_INTR_MASKED
0x40288F9C FULL Interrupt masked
DW0_CH_STRUCT62_SRAM_DATA0
0x40288FA0 FULL SRAM data 0
DW0_CH_STRUCT62_SRAM_DATA1
0x40288FA4 FULL SRAM data 1
DW0_CH_STRUCT62_TR_CMD
0x40288FA8 FULL Channel software trigger
9.1.1.64 CH_STRUCT 63
Register Name Address Permission Description
DW0_CH_STRUCT63_CH_CTL
0x40288FC0 FULL Channel control
DW0_CH_STRUCT63_CH_STATUS
0x40288FC4 FULL Channel status
DW0_CH_STRUCT63_CH_IDX
0x40288FC8 FULL Channel current indices
DW0_CH_STRUCT63_CH_CURR_PTR
0x40288FCC FULL Channel current descriptor pointer
DW0_CH_STRUCT63_INTR
0x40288FD0 FULL Interrupt
DW0_CH_STRUCT63_INTR_SET
0x40288FD4 FULL Interrupt set
DW0_CH_STRUCT63_INTR_MASK
0x40288FD8 FULL Interrupt mask
DW0_CH_STRUCT63_INTR_MASKED
0x40288FDC FULL Interrupt masked
DW0_CH_STRUCT63_SRAM_DATA0
0x40288FE0 FULL SRAM data 0
DW0_CH_STRUCT63_SRAM_DATA1
0x40288FE4 FULL SRAM data 1
DW0_CH_STRUCT63_TR_CMD
0x40288FE8 FULL Channel software trigger
9.1.1.65 CH_STRUCT 64
Register Name Address Permission Description
DW0_CH_STRUCT64_CH_CTL
0x40289000 FULL Channel control
DW0_CH_STRUCT64_CH_STATUS
0x40289004 FULL Channel status
DW0_CH_STRUCT64_CH_IDX
0x40289008 FULL Channel current indices
DW0_CH_STRUCT64_CH_CURR_PTR
0x4028900C FULL Channel current descriptor pointer
DW0_CH_STRUCT64_INTR
0x40289010 FULL Interrupt
DW0_CH_STRUCT64_INTR_SET
0x40289014 FULL Interrupt set
DW0_CH_STRUCT64_INTR_MASK
0x40289018 FULL Interrupt mask
DW0_CH_STRUCT64_INTR_MASKED
0x4028901C FULL Interrupt masked
DW0_CH_STRUCT64_SRAM_DATA0
0x40289020 FULL SRAM data 0
DW0_CH_STRUCT64_SRAM_DATA1
0x40289024 FULL SRAM data 1
DW0_CH_STRUCT64_TR_CMD
0x40289028 FULL Channel software trigger
9.1.1.66 CH_STRUCT 65
Register Name Address Permission Description
DW0_CH_STRUCT65_CH_CTL
0x40289040 FULL Channel control
DW0_CH_STRUCT65_CH_STATUS
0x40289044 FULL Channel status
DW0_CH_STRUCT65_CH_IDX
0x40289048 FULL Channel current indices
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers