Infineon TRAVEO T2G - 26.8.31 CLK_FLL_CONFIG2

Technical Reference Manual 002-29852 Rev. *B
26.8.31 CLK_FLL_CONFIG2
Description:
FLL Configuration Register 2
Address:
0x40261534
Offset:
0x1534
Retention:
Retained
IsDeepSleep:
Yes
Comment:
This register contains frequency lock loop (FLL) configuration. FLL circuit settings should not
be changed while it is a selected clock (connected to logic). This prevents clock glitches that
can crash the logic. Deselect the FLL using .BYPASS_SEL=FLL_REF
Default:
0x20001
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name FLL_REF_DIV [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:13] FLL_REF_DIV [12:8]
Bits 23 22 21 20 19 18 17 16
Name LOCK_TOL [23:16]
Bits 31 30 29 28 27 26 25 24
Name UPDATE_TOL [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:12 FLL_REF_DIV RW R 1 Control bits for reference divider. Set the divide value
before enabling the FLL, and do not change it while
FLL is enabled.
0: illegal (undefined behavior)
1: divide by 1
...
8191: divide by 8191
16:23 LOCK_TOL RW R 2 Lock tolerance sets the error threshold for when the
FLL output is considered locked to the reference input.
A high tolerance can be used to lock more quickly or
allow less accuracy. The tolerance is the allowed
difference between the count value for the ideal
formula and the measured value.
0: tolerate error of 1 count value
1: tolerate error of 2 count values
...
255: tolerate error of 256 count values
24:31 UPDATE_TOL RW R 0 Update tolerance sets the error threshold for when the
FLL will update the CCO frequency settings. The
update tolerance is the allowed difference between the
count value for the ideal formula and the measured
value. UPDATE_TOL should be less than LOCK_TOL.
1672
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers