Infineon TRAVEO T2G - 3.8.3.19 CM0 P_SCS_DFSR

Technical Reference Manual 002-29852 Rev. *B
3.8.3.19 CM0P_SCS_DFSR
Description:
Debug Fault Status Register
Address:
0xE000ED30
Offset:
0xD30
Retention:
Retained
IsDeepSleep:
No
Comment:
Provides the top level reason why a debug event has occurred. Writing 1 to a register bit
clears that bit to 0. A read of the HALTED bit by an instruction executed by stepping returns an
UNKNOWN value, For more information see Debug stepping on Arm TRM page C1-325.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:5] EXTERNAL
[4:4]
VCATCH
[3:3]
DWTTRAP
[2:2]
BKPT [1:1] HALTED
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 HALTED RW1C RW1S 0 Indicates a debug event generated by a C_HALT or
C_STEP request, triggered by a write to the DHCSR:
0 no active halt request debug event.
1 halt request debug event active.
See Debug Halting Control and Status Register,
DHCSR for more information.
1 BKPT RW1C RW1S 0 Indicates a debug event generated by BKPT
instruction execution or a breakpoint match in the
BPU:
0 no breakpoint debug event.
1 at least one breakpoint debug event.
2 DWTTRAP RW1C RW1S 0 Indicates a debug event generated by the DWT:
0 no debug events generated by the DWT.
1 at least one debug event generated by the DWT.
3 VCATCH RW1C RW1S 0 Indicates whether a vector catch debug event was
generated:
0 no vector catch debug event generated.
1 vector catch debug event generated.
The corresponding FSR shows the primary cause of
the exception.
4 EXTERNAL RW1C RW1S 0 Indicates an asynchronous debug event generated
because of EDBGRQ being asserted:
0 no EDBGRQ debug event.
1 EDBGRQ debug event.
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers