Infineon TRAVEO T2G - 15.25.7.8 GPIO_PRT_INTR_MASKED

Technical Reference Manual 002-29852 Rev. *B
15.25.7.8 GPIO_PRT_INTR_MASKED
Description:
Port interrupt masked status register
Address:
0x4031001C
Offset:
0x1C
Retention:
Retained
IsDeepSleep:
No
Comment:
This register contains the AND-ed values of INTR and INTR_MASK registers forwarded to the
CPU interrupt controller.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name EDGE7
[7:7]
EDGE6
[6:6]
EDGE5
[5:5]
EDGE4
[4:4]
EDGE3
[3:3]
EDGE2
[2:2]
EDGE1
[1:1]
EDGE0
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:9] FLT_EDGE
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 EDGE0 R W 0 Edge detected AND masked on IO pin 0
'0': Interrupt was not forwarded to CPU
'1': Interrupt occurred and was forwarded to CPU
1 EDGE1 R W 0 Edge detected and masked on IO pin 1
2 EDGE2 R W 0 Edge detected and masked on IO pin 2
3 EDGE3 R W 0 Edge detected and masked on IO pin 3
4 EDGE4 R W 0 Edge detected and masked on IO pin 4
5 EDGE5 R W 0 Edge detected and masked on IO pin 5
6 EDGE6 R W 0 Edge detected and masked on IO pin 6
7 EDGE7 R W 0 Edge detected and masked on IO pin 7
8 FLT_EDGE R W 0 Edge detected and masked on filtered pin selected by
INTR_CFG.FLT_SEL
1003
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers