Infineon TRAVEO T2G - 2.3.9.6.26 CANFD_CH_RXF0 C

Technical Reference Manual 002-29852 Rev. *B
2.3.9.6.26 CANFD_CH_RXF0C
Description:
Rx FIFO 0 Configuration
Address:
0x405200A0
Offset:
0xA0
Retention:
Retained
IsDeepSleep:
No
Comment:
Protected Write.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [1:0]
Bits 15 14 13 12 11 10 9 8
Name F0SA [15:8]
Bits 23 22 21 20 19 18 17 16
Name None
[23:23]
F0S [22:16]
Bits 31 30 29 28 27 26 25 24
Name F0OM
[31:31]
F0WM [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
2:15 F0SA RW R 0 Rx FIFO 0 Start Address
Start address of Rx FIFO 0 in Message RAM (32-bit
word address, see Figure 2).
16:22 F0S RW R 0 Rx FIFO 0 Size
0= No Rx FIFO 0
1-64= Number of Rx FIFO 0 elements
64= Values greater than 64 are interpreted as 64
The Rx FIFO 0 elements are indexed from 0 to F0S-1
24:30 F0WM RW R 0 Rx FIFO 0 Watermark
0= Watermark interrupt disabled
1-64= Level for Rx FIFO 0 watermark interrupt
(IR.RF0W)
64= Watermark interrupt disabled
31 F0OM RW R 0 FIFO 0 Operation Mode
FIFO 0 can be operated in blocking or in overwrite
mode (see Section 3.4.2).
0= FIFO 0 blocking mode
1= FIFO 0 overwrite mode
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers