Infineon TRAVEO T2G - 3.8.1.2 CM0 P_DWT_DWT_PCSR

Technical Reference Manual 002-29852 Rev. *B
3.8.1.2 CM0P_DWT_DWT_PCSR
Description:
Watchpoint Comparator PC Sample
Address:
0xE000101C
Offset:
0x1C
Retention:
Retained
IsDeepSleep:
No
Comment:
Samples the current value of the program counter. Unless DWT_PCSR reads as
0xFFFFFFFF, under the conditions described in Program counter sampling support on Arm
TRM page C1-344, bit [0] is RAZ. When RAZ, bit [0] does not reflect instruction set state as is
the case with similar functionality in
other ARM architecture profiles.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name EIASAMPLE [7:0]
Bits 15 14 13 12 11 10 9 8
Name EIASAMPLE [15:8]
Bits 23 22 21 20 19 18 17 16
Name EIASAMPLE [23:16]
Bits 31 30 29 28 27 26 25 24
Name EIASAMPLE [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 EIASAMPLE R W X Executed Instruction Address sample value
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2022-04-18
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