Infineon TRAVEO T2G - 9.1.1.80 CH_STRUCT 79; 9.1.1.81 CH_STRUCT 80; 9.1.1.82 CH_STRUCT 81; 9.1.1.83 CH_STRUCT 82

Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
DW0_CH_STRUCT78_TR_CMD
0x402893A8 FULL Channel software trigger
9.1.1.80 CH_STRUCT 79
Register Name Address Permission Description
DW0_CH_STRUCT79_CH_CTL
0x402893C0 FULL Channel control
DW0_CH_STRUCT79_CH_STATUS
0x402893C4 FULL Channel status
DW0_CH_STRUCT79_CH_IDX
0x402893C8 FULL Channel current indices
DW0_CH_STRUCT79_CH_CURR_PTR
0x402893CC FULL Channel current descriptor pointer
DW0_CH_STRUCT79_INTR
0x402893D0 FULL Interrupt
DW0_CH_STRUCT79_INTR_SET
0x402893D4 FULL Interrupt set
DW0_CH_STRUCT79_INTR_MASK
0x402893D8 FULL Interrupt mask
DW0_CH_STRUCT79_INTR_MASKED
0x402893DC FULL Interrupt masked
DW0_CH_STRUCT79_SRAM_DATA0
0x402893E0 FULL SRAM data 0
DW0_CH_STRUCT79_SRAM_DATA1
0x402893E4 FULL SRAM data 1
DW0_CH_STRUCT79_TR_CMD
0x402893E8 FULL Channel software trigger
9.1.1.81 CH_STRUCT 80
Register Name Address Permission Description
DW0_CH_STRUCT80_CH_CTL
0x40289400 FULL Channel control
DW0_CH_STRUCT80_CH_STATUS
0x40289404 FULL Channel status
DW0_CH_STRUCT80_CH_IDX
0x40289408 FULL Channel current indices
DW0_CH_STRUCT80_CH_CURR_PTR
0x4028940C FULL Channel current descriptor pointer
DW0_CH_STRUCT80_INTR
0x40289410 FULL Interrupt
DW0_CH_STRUCT80_INTR_SET
0x40289414 FULL Interrupt set
DW0_CH_STRUCT80_INTR_MASK
0x40289418 FULL Interrupt mask
DW0_CH_STRUCT80_INTR_MASKED
0x4028941C FULL Interrupt masked
DW0_CH_STRUCT80_SRAM_DATA0
0x40289420 FULL SRAM data 0
DW0_CH_STRUCT80_SRAM_DATA1
0x40289424 FULL SRAM data 1
DW0_CH_STRUCT80_TR_CMD
0x40289428 FULL Channel software trigger
9.1.1.82 CH_STRUCT 81
Register Name Address Permission Description
DW0_CH_STRUCT81_CH_CTL
0x40289440 FULL Channel control
DW0_CH_STRUCT81_CH_STATUS
0x40289444 FULL Channel status
DW0_CH_STRUCT81_CH_IDX
0x40289448 FULL Channel current indices
DW0_CH_STRUCT81_CH_CURR_PTR
0x4028944C FULL Channel current descriptor pointer
DW0_CH_STRUCT81_INTR
0x40289450 FULL Interrupt
DW0_CH_STRUCT81_INTR_SET
0x40289454 FULL Interrupt set
DW0_CH_STRUCT81_INTR_MASK
0x40289458 FULL Interrupt mask
DW0_CH_STRUCT81_INTR_MASKED
0x4028945C FULL Interrupt masked
DW0_CH_STRUCT81_SRAM_DATA0
0x40289460 FULL SRAM data 0
DW0_CH_STRUCT81_SRAM_DATA1
0x40289464 FULL SRAM data 1
DW0_CH_STRUCT81_TR_CMD
0x40289468 FULL Channel software trigger
9.1.1.83 CH_STRUCT 82
Register Name Address Permission Description
DW0_CH_STRUCT82_CH_CTL
0x40289480 FULL Channel control
DW0_CH_STRUCT82_CH_STATUS
0x40289484 FULL Channel status
DW0_CH_STRUCT82_CH_IDX
0x40289488 FULL Channel current indices
DW0_CH_STRUCT82_CH_CURR_PTR
0x4028948C FULL Channel current descriptor pointer
DW0_CH_STRUCT82_INTR
0x40289490 FULL Interrupt
DW0_CH_STRUCT82_INTR_SET
0x40289494 FULL Interrupt set
DW0_CH_STRUCT82_INTR_MASK
0x40289498 FULL Interrupt mask
DW0_CH_STRUCT82_INTR_MASKED
0x4028949C FULL Interrupt masked
DW0_CH_STRUCT82_SRAM_DATA0
0x402894A0 FULL SRAM data 0
DW0_CH_STRUCT82_SRAM_DATA1
0x402894A4 FULL SRAM data 1
DW0_CH_STRUCT82_TR_CMD
0x402894A8 FULL Channel software trigger
9.1.1.84 CH_STRUCT 83
Register Name Address Permission Description
DW0_CH_STRUCT83_CH_CTL
0x402894C0 FULL Channel control
DW0_CH_STRUCT83_CH_STATUS
0x402894C4 FULL Channel status
DW0_CH_STRUCT83_CH_IDX
0x402894C8 FULL Channel current indices
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