Infineon TRAVEO T2G - 19.5.1.18.5 PASS_SAR_CH_INTR

Technical Reference Manual 002-29852 Rev. *B
19.5.1.18.5 PASS_SAR_CH_INTR
Description:
Interrupt request register.
Address:
0x40900810
Offset:
0x10
Retention:
Not Retained
IsDeepSleep:
No
Comment:
interrupts for one channel
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:3] GRP
_OVERF
LOW [2:2]
GRP
_CANCE
LLED [1:1]
GRP
_DONE
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:11] CH
_OVERFL
OW [10:10]
CH_PULSE
[9:9]
CH
_RANGE
[8:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 GRP_DONE RW1C RW1S 0 Done Interrupt: hardware sets this interrupt for the last
channel of a group if the group scan is done. Write
with '1' to clear bit.
1 GRP_CANCELLED RW1C RW1S 0 Cancelled Interrupt: hardware sets this interrupt for the
last channel of a group if the group scan was
preempted and CANCELLED. Note that it is possible
that also the GRP_DONE interrupt is set. If that is the
case one or more new triggers were detected while the
group was already busy, i.e. triggers are too fast. Write
with '1' to clear bit.
2 GRP_OVERFLOW RW1C RW1S 0 Overflow Interrupt: hardware sets this interrupt for the
last channel of a group if the group scan is done and
the Done interrupt is already (still) pending. Write with
'1' to clear bit.
8 CH_RANGE RW1C RW1S 0 Range detect Interrupt: hardware sets this interrupt for
each channel if the conversion result (after averaging)
of that channel met the condition specified by the
SAR_RANGE registers. This interrupt is mutual
exclusive with Pulse detect interrupt. Write with '1' to
clear bit.
9 CH_PULSE RW1C RW1S 0 Pulse detect Interrupt: hardware sets this interrupt for
each channel if the positive pulse counter reaches
zero. This interrupt is mutual exclusive with Range
detect interrupt. Write with '1' to clear bit.
10 CH_OVERFLOW RW1C RW1S 0 Channel overflow Interrupt: hardware sets this interrupt
for each channel if a new Pulse or Range interrupt is
detected while the interrupt is still pending or when DW
did not acknowledge data pickup. Write with '1' to clear
bit.
1115
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers