Infineon TRAVEO T2G - 5.1.31 CPUSS_RAM0_STATUS

Technical Reference Manual 002-29852 Rev. *B
5.1.31 CPUSS_RAM0_STATUS
Description:
RAM 0 status
Address:
0x40201304
Offset:
0x1304
Retention:
Retained
IsDeepSleep:
No
Comment:
This register is for the CPUSS system SRAM controller 0.
Default:
0x1
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] WB
_EMPTY
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 WB_EMPTY R W 1 Write buffer empty. This information is used when
entering DeepSleep power mode: WB_EMPTY must
be '1' before a transition to system DeepSleep power
mode.
'0': Write buffer NOT empty.
'1': Write buffer empty.
Note: the SRAM controller write buffer is only used
when ECC checking is enabled. (RAMi_CTL.ECC_EN
is '1').
733
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers