Infineon TRAVEO T2G - 9.1.1.49 CH_STRUCT 48; 9.1.1.50 CH_STRUCT 49; 9.1.1.51 CH_STRUCT 50; 9.1.1.52 CH_STRUCT 51

Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
DW0_CH_STRUCT47_CH_CURR_PTR
0x40288BCC FULL Channel current descriptor pointer
DW0_CH_STRUCT47_INTR
0x40288BD0 FULL Interrupt
DW0_CH_STRUCT47_INTR_SET
0x40288BD4 FULL Interrupt set
DW0_CH_STRUCT47_INTR_MASK
0x40288BD8 FULL Interrupt mask
DW0_CH_STRUCT47_INTR_MASKED
0x40288BDC FULL Interrupt masked
DW0_CH_STRUCT47_SRAM_DATA0
0x40288BE0 FULL SRAM data 0
DW0_CH_STRUCT47_SRAM_DATA1
0x40288BE4 FULL SRAM data 1
DW0_CH_STRUCT47_TR_CMD
0x40288BE8 FULL Channel software trigger
9.1.1.49 CH_STRUCT 48
Register Name Address Permission Description
DW0_CH_STRUCT48_CH_CTL
0x40288C00 FULL Channel control
DW0_CH_STRUCT48_CH_STATUS
0x40288C04 FULL Channel status
DW0_CH_STRUCT48_CH_IDX
0x40288C08 FULL Channel current indices
DW0_CH_STRUCT48_CH_CURR_PTR
0x40288C0C FULL Channel current descriptor pointer
DW0_CH_STRUCT48_INTR
0x40288C10 FULL Interrupt
DW0_CH_STRUCT48_INTR_SET
0x40288C14 FULL Interrupt set
DW0_CH_STRUCT48_INTR_MASK
0x40288C18 FULL Interrupt mask
DW0_CH_STRUCT48_INTR_MASKED
0x40288C1C FULL Interrupt masked
DW0_CH_STRUCT48_SRAM_DATA0
0x40288C20 FULL SRAM data 0
DW0_CH_STRUCT48_SRAM_DATA1
0x40288C24 FULL SRAM data 1
DW0_CH_STRUCT48_TR_CMD
0x40288C28 FULL Channel software trigger
9.1.1.50 CH_STRUCT 49
Register Name Address Permission Description
DW0_CH_STRUCT49_CH_CTL
0x40288C40 FULL Channel control
DW0_CH_STRUCT49_CH_STATUS
0x40288C44 FULL Channel status
DW0_CH_STRUCT49_CH_IDX
0x40288C48 FULL Channel current indices
DW0_CH_STRUCT49_CH_CURR_PTR
0x40288C4C FULL Channel current descriptor pointer
DW0_CH_STRUCT49_INTR
0x40288C50 FULL Interrupt
DW0_CH_STRUCT49_INTR_SET
0x40288C54 FULL Interrupt set
DW0_CH_STRUCT49_INTR_MASK
0x40288C58 FULL Interrupt mask
DW0_CH_STRUCT49_INTR_MASKED
0x40288C5C FULL Interrupt masked
DW0_CH_STRUCT49_SRAM_DATA0
0x40288C60 FULL SRAM data 0
DW0_CH_STRUCT49_SRAM_DATA1
0x40288C64 FULL SRAM data 1
DW0_CH_STRUCT49_TR_CMD
0x40288C68 FULL Channel software trigger
9.1.1.51 CH_STRUCT 50
Register Name Address Permission Description
DW0_CH_STRUCT50_CH_CTL
0x40288C80 FULL Channel control
DW0_CH_STRUCT50_CH_STATUS
0x40288C84 FULL Channel status
DW0_CH_STRUCT50_CH_IDX
0x40288C88 FULL Channel current indices
DW0_CH_STRUCT50_CH_CURR_PTR
0x40288C8C FULL Channel current descriptor pointer
DW0_CH_STRUCT50_INTR
0x40288C90 FULL Interrupt
DW0_CH_STRUCT50_INTR_SET
0x40288C94 FULL Interrupt set
DW0_CH_STRUCT50_INTR_MASK
0x40288C98 FULL Interrupt mask
DW0_CH_STRUCT50_INTR_MASKED
0x40288C9C FULL Interrupt masked
DW0_CH_STRUCT50_SRAM_DATA0
0x40288CA0 FULL SRAM data 0
DW0_CH_STRUCT50_SRAM_DATA1
0x40288CA4 FULL SRAM data 1
DW0_CH_STRUCT50_TR_CMD
0x40288CA8 FULL Channel software trigger
9.1.1.52 CH_STRUCT 51
Register Name Address Permission Description
DW0_CH_STRUCT51_CH_CTL
0x40288CC0 FULL Channel control
DW0_CH_STRUCT51_CH_STATUS
0x40288CC4 FULL Channel status
DW0_CH_STRUCT51_CH_IDX
0x40288CC8 FULL Channel current indices
DW0_CH_STRUCT51_CH_CURR_PTR
0x40288CCC FULL Channel current descriptor pointer
DW0_CH_STRUCT51_INTR
0x40288CD0 FULL Interrupt
DW0_CH_STRUCT51_INTR_SET
0x40288CD4 FULL Interrupt set
DW0_CH_STRUCT51_INTR_MASK
0x40288CD8 FULL Interrupt mask
DW0_CH_STRUCT51_INTR_MASKED
0x40288CDC FULL Interrupt masked
DW0_CH_STRUCT51_SRAM_DATA0
0x40288CE0 FULL SRAM data 0
DW0_CH_STRUCT51_SRAM_DATA1
0x40288CE4 FULL SRAM data 1
838
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