Technical Reference Manual 002-29852 Rev. *B
26.8.50.11 CTR
26.8.50.11.1 MCWDT_CTR_CTL
Description:
MCWDT Subcounter Control Register
Address:
0x40268000
Offset:
0x0
Retention:
Retained
IsDeepSleep:
Yes
Comment:
Control register for this MCWDT subcounter. Writes are ignored when locked (i.e.
corresponding MCWDT[i]_LOCK.WDT_LOCK<>0). This register may be written while the
counter is running, but new values may take up to 2 clk_lf cycles to take effect.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] ENABLED
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLE
[31:31]
None [30:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 ENABLED R RW 0 Indicates actual state of this subcounter. May lag
ENABLE by up to two clk_lf cycles.
31 ENABLE RW R 0 Enable subcounter. May take up to 2 clk_lf cycles to
take effect. When ENABLE changes from 1->0, the
counter is cleared.
0: Counter is disabled (not clocked)
1: Counter is enabled (counting up)
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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