Technical Reference Manual 002-29852 Rev. *B
26.8.51.9 WDT_INTR
Description:
WDT Interrupt Register
Address:
0x4026C050
Offset:
0x50
Retention:
Retained
IsDeepSleep:
No
Comment:
Interrupt signal from WDT
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] WDT [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 WDT RW1C A 0 WDT Interrupt Request. This bit is set as configured by
WDT action and limits. Due to internal synchronization,
it takes up to 8 SYSCLK cycles to update after a W1C
or reading this register and during this time AHB bus is
stalled.
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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