Infineon TRAVEO T2G - 26.8.32 CLK_FLL_CONFIG3

Technical Reference Manual 002-29852 Rev. *B
26.8.32 CLK_FLL_CONFIG3
Description:
FLL Configuration Register 3
Address:
0x40261538
Offset:
0x1538
Retention:
Retained
IsDeepSleep:
Yes
Comment:
This register contains frequency lock loop (FLL) configuration. Do not change settings while
the FLL is running, except BYPASS_SEL.
Default:
0x2800
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name FLL_LF_PGAIN [7:4] FLL_LF_IGAIN [3:0]
Bits 15 14 13 12 11 10 9 8
Name SETTLING_COUNT [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:21] SETTLING_COUNT [20:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:30] BYPASS_SEL [29:28] None [27:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:3 FLL_LF_IGAIN RW R 0 FLL Loop Filter Gain Setting #1. The proportional gain
is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN.
0: 1/256
1: 1/128
2: 1/64
3: 1/32
4: 1/16
5: 1/8
6: 1/4
7: 1/2
8: 1.0
9: 2.0
10: 4.0
11: 8.0
>=12: illegal
4:7 FLL_LF_PGAIN RW R 0 FLL Loop Filter Gain Setting #2. The proportional gain
is the sum of FLL_LF_IGAIN and FLL_LF_PGAIN.
0: 1/256
1: 1/128
2: 1/64
3: 1/32
4: 1/16
5: 1/8
6: 1/4
7: 1/2
8: 1.0
9: 2.0
10: 4.0
11: 8.0
>=12: illegal
1673
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers