Technical Reference Manual 002-29852 Rev. *B
9.3.15 DW_CRC_LFSR_CTL
Description:
CRC LFSR control
Address:
0x40280130
Offset:
0x130
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name LFSR32 [7:0]
Bits 15 14 13 12 11 10 9 8
Name LFSR32 [15:8]
Bits 23 22 21 20 19 18 17 16
Name LFSR32 [23:16]
Bits 31 30 29 28 27 26 25 24
Name LFSR32 [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 LFSR32 RW RW 0 State of a 32-bit Linear Feedback Shift Registers
(LFSR) that is used to implement CRC. This register
needs to be initialized by SW to provide the CRC seed
value.
The seed value should be aligned such that the more
significant bits (bit 31 and down) contain the seed
value and the less significant bits (bit 0 and up) contain
padding '0's.
Note that SW can write this field. This functionality can
be used prevent information leakage (through either
CRC_LFSR_CTL or CRC_REM_RESULT).
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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