Technical Reference Manual 002-29852 Rev. *B
9.3.18.2 DW_CH_STRUCT_CH_STATUS
Description:
Channel status
Address:
0x40288004
Offset:
0x4
Retention:
Not Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:4] INTR_CAUSE [3:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name PENDING
[31:31]
None [30:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:3 INTR_CAUSE R W Undefined Specifies the source of the interrupt cause:
'0': No interrupt generated
'1': Interrupt based on transfer complettion
configuration based on INTR_TYPE
'2': Source transfer bus error
'3': Destination transfer bus error
'4': Source address misalignment
'5': Destination address misalignment
'6': Current descriptor pointer is null
'7': Active channel is disabled
'8': Descriptor bus error
'9'-'15': Not used.
For error related interrupt causes (INTR_CAUSE is '2',
'3', ..., '8'), the channel is disabled (HW sets
CH_CTL.ENABLED to '0').
31 PENDING R W 0 Specifies pending DW channels; i.e. enabled channels
whose trigger got activated. This field includes all
channels that are in the pending state (not scheduled)
or active state (scheduled and performing data
transfer(s)).
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers
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