Infineon TRAVEO T2G - 18.13.3.7 LIN_CH_DATA0

Technical Reference Manual 002-29852 Rev. *B
18.13.3.7 LIN_CH_DATA0
Description:
Response data 0
Address:
0x40508084
Offset:
0x84
Retention:
Retained
IsDeepSleep:
No
Comment:
This register supports 8-bit, 16-bit and 32-bit accesses. This allows for a single 32-bit access
to write or read four data fields.
A LIN response has a maximum of eight data fields. These data fields are SW accessible
through the DATA0 and DATA1 registers. These register are used in BOTH transmit and
receive modes. If the LIN response is both transmitted and received, the to be transmitted
data fields (provided by SW) in this register are overwritten by the received data fields
(provided by HW).
Data field DATA1 is the first response data field (first to be transmitted/received). The number
of transmitted/received data fields is specified by CTL.DATA_NR.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name DATA1 [7:0]
Bits 15 14 13 12 11 10 9 8
Name DATA2 [15:8]
Bits 23 22 21 20 19 18 17 16
Name DATA3 [23:16]
Bits 31 30 29 28 27 26 25 24
Name DATA4 [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 DATA1 RW RW Undefined Data field 1.
Transmission: To be transmitted data field. SW
provides data field.
Reception: Received data field. SW uses the data
field.
8:15 DATA2 RW RW Undefined Data field 2.
16:23 DATA3 RW RW Undefined Data field 3.
24:31 DATA4 RW RW Undefined Data field 4.
1059
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers