Infineon TRAVEO T2G - 20.30.3 PERI_DIV_CMD

Technical Reference Manual 002-29852 Rev. *B
20.30.3 PERI_DIV_CMD
Description:
Divider command
Address:
0x40000400
Offset:
0x400
Retention:
Not Retained
IsDeepSleep:
No
Comment:
The (PA_TYPE_SEL, PA_DIV_SEL) field pair allows a divider to be phase aligned with
another divider. E.g., consider a 48 MHz 'clk_peri', and a need for a 12 MHz divided clock A
and a 8 MHz divided clock B. Clock A uses 8.0 integer divider 0 and is created by aligning it to
'clk_peri' ((PA_TYPE_SEL, PA_DIV_SEL) is (3, 63)) and DIV_8_CTL0.INT8_DIV is '4-1'.
Clock B uses 8.0 integer divider 1 and is created by aligning it to clock A ((PA_TYPE_SEL,
PA_DIV_SEL) is (0, 0)) and DIV_8_CTL1.INT8_DIV is '6-1'. This guarantees that clock B is
phase aligned with clock A: as the smallest common multiple of the two clock periods is 12
'clk_peri' cycles, the clocks A and B will be aligned every 12 'clk_peri' cycles. Note: clock B is
phase aligned to clock A, but still uses 'clk_peri' as a reference clock for its divider value.
Default:
0x3FF03FF
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name DIV_SEL [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:10] TYPE_SEL [9:8]
Bits 23 22 21 20 19 18 17 16
Name PA_DIV_SEL [23:16]
Bits 31 30 29 28 27 26 25 24
Name ENABLE
[31:31]
DISABLE
[30:30]
None [29:26] PA_TYPE_SEL [25:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 DIV_SEL RW R 255 (TYPE_SEL, DIV_SEL) specifies the divider on which
the command (DISABLE/ENABLE) is performed.
If DIV_SEL is '255' and TYPE_SEL is '3' (default/reset
value), no divider is specified and no clock signal(s)
are generated.
8:9 TYPE_SEL RW R 3 Specifies the divider type of the divider on which the
command is performed:
0: 8.0 (integer) clock dividers.
1: 16.0 (integer) clock dividers.
2: 16.5 (fractional) clock dividers.
3: 24.5 (fractional) clock dividers.
16:23 PA_DIV_SEL RW R 255 (PA_TYPE_SEL, PA_DIV_SEL) specifies the divider to
which phase alignment is performed for the clock
enable command. Any enabled divider can be used as
reference. This allows all dividers to be aligned with
each other, even when they are enabled at different
times.
If PA_DIV_SEL is '255' and PA_TYPE_SEL is '3',
'clk_peri' is used as reference.
1143
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers