Infineon TRAVEO T2G - 14.2.17 FLASHC_CM4_CA_CTL1

Technical Reference Manual 002-29852 Rev. *B
14.2.17 FLASHC_CM4_CA_CTL1
Description:
CM4 cache control
Address:
0x40240484
Offset:
0x484
Retention:
Retained
IsDeepSleep:
No
Comment:
This register controls the CM4 Cache SRAM power states. CM4 Cache SRAM consists of a
single power partition.
Default:
0xFA050003
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:2] PWR_MODE [1:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name VECTKEYSTAT [23:16]
Bits 31 30 29 28 27 26 25 24
Name VECTKEYSTAT [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:1 PWR_MODE RW R 3 Specifies power mode for CM4 cache.
The following sequnece should be followed for truning
OFF/ON the cache SRAM.
Turn OFF sequence:
a) Write CM4_CA_CTL0 to disable cache.
b) Write CM4_CA_CTL1 to turn OFF cache SRAM.
Turn ON sequence:
a) Write CM4_CA_CTL1 to turn ON cache SRAM.
b) Delay to allow power up of cache SRAM. Delay
should be at a minimum of
CM4_CA_CTL2.PWRUP_DELAY CLK_SLOW clock
cycles.
c) Write CM4_CA_CTL0 to enable cache.
OFF 0 Power OFF the CM4 cache, not retained.
RESERVED 1 Undefined
RETAINED 2 Put the CM4 cache in retained mode.
ENABLED 3 Enable/Turn ON the CM4 cache.
16:31 VECTKEYSTAT R 64005 Register key (to prevent accidental writes).
- Should be written with a 0x05fa key value for the
write to take effect.
- Always reads as 0xfa05.
Note: Although the SW attribute for this field says ''R',
SW need to write the key 0x05fa in this field for this
register write to happen. This is a built in protection
provided to prevent accidental writes from SW.
954
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers