Infineon TRAVEO T2G - 19.1.16 CH 15; 19.1.17 CH 16; 19.1.18 CH 17; 19.1.19 CH 18

Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
PASS0_SAR0_CH14_TR_CTL
0x40900B80 FULL Trigger control.
PASS0_SAR0_CH14_SAMPLE_CTL
0x40900B84 FULL Sample control.
PASS0_SAR0_CH14_POST_CTL
0x40900B88 FULL Post processing control
PASS0_SAR0_CH14_RANGE_CTL
0x40900B8C FULL Range thresholds
PASS0_SAR0_CH14_INTR
0x40900B90 FULL Interrupt request register.
PASS0_SAR0_CH14_INTR_SET
0x40900B94 FULL Interrupt set request register
PASS0_SAR0_CH14_INTR_MASK
0x40900B98 FULL Interrupt mask register.
PASS0_SAR0_CH14_INTR_MASKED
0x40900B9C FULL Interrupt masked request register
PASS0_SAR0_CH14_WORK
0x40900BA0 FULL Working data register
PASS0_SAR0_CH14_RESULT
0x40900BA4 FULL Result data register
PASS0_SAR0_CH14_GRP_STAT
0x40900BA8 FULL Group status register
PASS0_SAR0_CH14_ENABLE
0x40900BB8 FULL Enable register
PASS0_SAR0_CH14_TR_CMD
0x40900BBC FULL Software triggers
19.1.16 CH 15
Register Name Address Permission Description
PASS0_SAR0_CH15_TR_CTL
0x40900BC0 FULL Trigger control.
PASS0_SAR0_CH15_SAMPLE_CTL
0x40900BC4 FULL Sample control.
PASS0_SAR0_CH15_POST_CTL
0x40900BC8 FULL Post processing control
PASS0_SAR0_CH15_RANGE_CTL
0x40900BCC FULL Range thresholds
PASS0_SAR0_CH15_INTR
0x40900BD0 FULL Interrupt request register.
PASS0_SAR0_CH15_INTR_SET
0x40900BD4 FULL Interrupt set request register
PASS0_SAR0_CH15_INTR_MASK
0x40900BD8 FULL Interrupt mask register.
PASS0_SAR0_CH15_INTR_MASKED
0x40900BDC FULL Interrupt masked request register
PASS0_SAR0_CH15_WORK
0x40900BE0 FULL Working data register
PASS0_SAR0_CH15_RESULT
0x40900BE4 FULL Result data register
PASS0_SAR0_CH15_GRP_STAT
0x40900BE8 FULL Group status register
PASS0_SAR0_CH15_ENABLE
0x40900BF8 FULL Enable register
PASS0_SAR0_CH15_TR_CMD
0x40900BFC FULL Software triggers
19.1.17 CH 16
Register Name Address Permission Description
PASS0_SAR0_CH16_TR_CTL
0x40900C00 FULL Trigger control.
PASS0_SAR0_CH16_SAMPLE_CTL
0x40900C04 FULL Sample control.
PASS0_SAR0_CH16_POST_CTL
0x40900C08 FULL Post processing control
PASS0_SAR0_CH16_RANGE_CTL
0x40900C0C FULL Range thresholds
PASS0_SAR0_CH16_INTR
0x40900C10 FULL Interrupt request register.
PASS0_SAR0_CH16_INTR_SET
0x40900C14 FULL Interrupt set request register
PASS0_SAR0_CH16_INTR_MASK
0x40900C18 FULL Interrupt mask register.
PASS0_SAR0_CH16_INTR_MASKED
0x40900C1C FULL Interrupt masked request register
PASS0_SAR0_CH16_WORK
0x40900C20 FULL Working data register
PASS0_SAR0_CH16_RESULT
0x40900C24 FULL Result data register
PASS0_SAR0_CH16_GRP_STAT
0x40900C28 FULL Group status register
PASS0_SAR0_CH16_ENABLE
0x40900C38 FULL Enable register
PASS0_SAR0_CH16_TR_CMD
0x40900C3C FULL Software triggers
19.1.18 CH 17
Register Name Address Permission Description
PASS0_SAR0_CH17_TR_CTL
0x40900C40 FULL Trigger control.
PASS0_SAR0_CH17_SAMPLE_CTL
0x40900C44 FULL Sample control.
PASS0_SAR0_CH17_POST_CTL
0x40900C48 FULL Post processing control
PASS0_SAR0_CH17_RANGE_CTL
0x40900C4C FULL Range thresholds
PASS0_SAR0_CH17_INTR
0x40900C50 FULL Interrupt request register.
PASS0_SAR0_CH17_INTR_SET
0x40900C54 FULL Interrupt set request register
PASS0_SAR0_CH17_INTR_MASK
0x40900C58 FULL Interrupt mask register.
PASS0_SAR0_CH17_INTR_MASKED
0x40900C5C FULL Interrupt masked request register
PASS0_SAR0_CH17_WORK
0x40900C60 FULL Working data register
PASS0_SAR0_CH17_RESULT
0x40900C64 FULL Result data register
PASS0_SAR0_CH17_GRP_STAT
0x40900C68 FULL Group status register
PASS0_SAR0_CH17_ENABLE
0x40900C78 FULL Enable register
PASS0_SAR0_CH17_TR_CMD
0x40900C7C FULL Software triggers
19.1.19 CH 18
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers