Infineon TRAVEO T2G - 22.5.2.3 MPU_STRUCT; 22.5.2.3.1 PROT_MPU_MPU_STRUCT_ADDR

Technical Reference Manual 002-29852 Rev. *B
22.5.2.3 MPU_STRUCT
22.5.2.3.1 PROT_MPU_MPU_STRUCT_ADDR
Description:
MPU region address
Address:
0x40234200
Offset:
0x0
Retention:
Retained
IsDeepSleep:
No
Comment:
This register defines a MPU address region.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name SUBREGION_DISABLE [7:0]
Bits 15 14 13 12 11 10 9 8
Name ADDR24 [15:8]
Bits 23 22 21 20 19 18 17 16
Name ADDR24 [23:16]
Bits 31 30 29 28 27 26 25 24
Name ADDR24 [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 SUBREGION_DISABLE RW R Undefined This field is used to individually disabled the eight
equally sized subregions in which a region is
partitioned. Subregion disable:
Bit 0: subregion 0 disable.
Bit 1: subregion 1 disable.
Bit 2: subregion 2 disable.
Bit 3: subregion 3 disable.
Bit 4: subregion 4 disable.
Bit 5: subregion 5 disable.
Bit 6: subregion 6 disable.
Bit 7: subregion 7 disable.
E.g., a 64 KByte address region (REGION_SIZE is
'15') has eight 8 KByte subregions. The access control
as defined by MPU_REGION_ATT applies if the bus
transfer address is within the address region AND the
addressed subregion is NOT disabled. Note that the
smallest region size is 256 B and the smallest
subregion size is 32 B.
8:31 ADDR24 RW R Undefined This field specifies the most significant bits of the 32-
bit address of an address region. The region size is
defined by ATT.REGION_SIZE. A region of n Byte is
always n Byte aligned. As a result, some of the lesser
significant address bits of ADDR24 may be ignored in
determining whether a bus transfer address is within
an address region. E.g., a 64 KByte address region
(REGION_SIZE is '15') is 64 KByte aligned, and
ADDR24[7:0] are ignored.
1337
2022-04-18
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