Infineon TRAVEO T2G - 26.8.10 SRSS_INTR_MASK

Technical Reference Manual 002-29852 Rev. *B
26.8.10 SRSS_INTR_MASK
Description:
SRSS Interrupt Mask Register
Address:
0x40260208
Offset:
0x208
Retention:
Retained
IsDeepSleep:
Yes
Comment:
Controls whether interrupt is forwarded to CPU. All masks block the interrupt when 0 and
forward the interrupt when 1
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:6] CLK_CAL
[5:5]
None [4:3] HVLVD2
[2:2]
HVLVD1
[1:1]
None [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
1 HVLVD1 RW R 0 Mask for low voltage detector HVLVD1
2 HVLVD2 RW R 0 Mask for low voltage detector HVLVD2
5 CLK_CAL RW R 0 Mask for clock calibration done
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2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers