Infineon TRAVEO T2G - 3.8.3.22 CM0 P_SCS_MPU_RNR

Technical Reference Manual 002-29852 Rev. *B
3.8.3.22 CM0P_SCS_MPU_RNR
Description:
MPU Region Number Register
Address:
0xE000ED98
Offset:
0xD98
Retention:
Retained
IsDeepSleep:
No
Comment:
Selects the region currently accessed by MPU_RBAR and MPU_RASR.
Used with MPU_RBAR and MPU_RASR, see MPU Region Base Address Register,
MPU_RBAR, and MPU Region Attribute and Size Register, MPU_RASR.
If an implementation supports N regions then the regions number from 0 to (N-1), and the
effect of writing a value of N or greater to the REGION field is UNPREDICTABLE.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name REGION_M [7:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:7 REGION_M RW R X Indicates the memory region accessed by MPU_RBAR
and MPU_RSAR.
Normally, software must write the required region
number to MPU_RNR to select the required memory
region, before accessing MPU_RBAR or MPU_RSAR.
However, the MPU_RBAR.VALID bit provides an
alternative way of writing to MPU_RBAR to update a
region base address without first writing the region
number to MPU_RNR, see MPU Region Base Address
Register, MPU_RBAR.
183
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers