Infineon TRAVEO T2G - 13.5.1.12 FAULT_STRUCT_INTR_MASK

Technical Reference Manual 002-29852 Rev. *B
13.5.1.12 FAULT_STRUCT_INTR_MASK
Description:
Interrupt mask
Address:
0x402100C8
Offset:
0xC8
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:1] FAULT [0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0 FAULT RW R 0 Mask bit for corresponding field in the INTR register.
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2022-04-18
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