Technical Reference Manual 002-29852 Rev. *B
Register Name Address Permission Description
DW0_CH_STRUCT42_TR_CMD
0x40288AA8 FULL Channel software trigger
9.1.1.44 CH_STRUCT 43
Register Name Address Permission Description
DW0_CH_STRUCT43_CH_CTL
0x40288AC0 FULL Channel control
DW0_CH_STRUCT43_CH_STATUS
0x40288AC4 FULL Channel status
DW0_CH_STRUCT43_CH_IDX
0x40288AC8 FULL Channel current indices
DW0_CH_STRUCT43_CH_CURR_PTR
0x40288ACC FULL Channel current descriptor pointer
DW0_CH_STRUCT43_INTR
0x40288AD0 FULL Interrupt
DW0_CH_STRUCT43_INTR_SET
0x40288AD4 FULL Interrupt set
DW0_CH_STRUCT43_INTR_MASK
0x40288AD8 FULL Interrupt mask
DW0_CH_STRUCT43_INTR_MASKED
0x40288ADC FULL Interrupt masked
DW0_CH_STRUCT43_SRAM_DATA0
0x40288AE0 FULL SRAM data 0
DW0_CH_STRUCT43_SRAM_DATA1
0x40288AE4 FULL SRAM data 1
DW0_CH_STRUCT43_TR_CMD
0x40288AE8 FULL Channel software trigger
9.1.1.45 CH_STRUCT 44
Register Name Address Permission Description
DW0_CH_STRUCT44_CH_CTL
0x40288B00 FULL Channel control
DW0_CH_STRUCT44_CH_STATUS
0x40288B04 FULL Channel status
DW0_CH_STRUCT44_CH_IDX
0x40288B08 FULL Channel current indices
DW0_CH_STRUCT44_CH_CURR_PTR
0x40288B0C FULL Channel current descriptor pointer
DW0_CH_STRUCT44_INTR
0x40288B10 FULL Interrupt
DW0_CH_STRUCT44_INTR_SET
0x40288B14 FULL Interrupt set
DW0_CH_STRUCT44_INTR_MASK
0x40288B18 FULL Interrupt mask
DW0_CH_STRUCT44_INTR_MASKED
0x40288B1C FULL Interrupt masked
DW0_CH_STRUCT44_SRAM_DATA0
0x40288B20 FULL SRAM data 0
DW0_CH_STRUCT44_SRAM_DATA1
0x40288B24 FULL SRAM data 1
DW0_CH_STRUCT44_TR_CMD
0x40288B28 FULL Channel software trigger
9.1.1.46 CH_STRUCT 45
Register Name Address Permission Description
DW0_CH_STRUCT45_CH_CTL
0x40288B40 FULL Channel control
DW0_CH_STRUCT45_CH_STATUS
0x40288B44 FULL Channel status
DW0_CH_STRUCT45_CH_IDX
0x40288B48 FULL Channel current indices
DW0_CH_STRUCT45_CH_CURR_PTR
0x40288B4C FULL Channel current descriptor pointer
DW0_CH_STRUCT45_INTR
0x40288B50 FULL Interrupt
DW0_CH_STRUCT45_INTR_SET
0x40288B54 FULL Interrupt set
DW0_CH_STRUCT45_INTR_MASK
0x40288B58 FULL Interrupt mask
DW0_CH_STRUCT45_INTR_MASKED
0x40288B5C FULL Interrupt masked
DW0_CH_STRUCT45_SRAM_DATA0
0x40288B60 FULL SRAM data 0
DW0_CH_STRUCT45_SRAM_DATA1
0x40288B64 FULL SRAM data 1
DW0_CH_STRUCT45_TR_CMD
0x40288B68 FULL Channel software trigger
9.1.1.47 CH_STRUCT 46
Register Name Address Permission Description
DW0_CH_STRUCT46_CH_CTL
0x40288B80 FULL Channel control
DW0_CH_STRUCT46_CH_STATUS
0x40288B84 FULL Channel status
DW0_CH_STRUCT46_CH_IDX
0x40288B88 FULL Channel current indices
DW0_CH_STRUCT46_CH_CURR_PTR
0x40288B8C FULL Channel current descriptor pointer
DW0_CH_STRUCT46_INTR
0x40288B90 FULL Interrupt
DW0_CH_STRUCT46_INTR_SET
0x40288B94 FULL Interrupt set
DW0_CH_STRUCT46_INTR_MASK
0x40288B98 FULL Interrupt mask
DW0_CH_STRUCT46_INTR_MASKED
0x40288B9C FULL Interrupt masked
DW0_CH_STRUCT46_SRAM_DATA0
0x40288BA0 FULL SRAM data 0
DW0_CH_STRUCT46_SRAM_DATA1
0x40288BA4 FULL SRAM data 1
DW0_CH_STRUCT46_TR_CMD
0x40288BA8 FULL Channel software trigger
9.1.1.48 CH_STRUCT 47
Register Name Address Permission Description
DW0_CH_STRUCT47_CH_CTL
0x40288BC0 FULL Channel control
DW0_CH_STRUCT47_CH_STATUS
0x40288BC4 FULL Channel status
DW0_CH_STRUCT47_CH_IDX
0x40288BC8 FULL Channel current indices
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers