Infineon TRAVEO T2G - 4.13.4.7 CM4_SCS_NVIC_ICER

Technical Reference Manual 002-29852 Rev. *B
4.13.4.7 CM4_SCS_NVIC_ICER
Description:
Interrupt Clear-Enable Registers
Address:
0xE000E180
Offset:
0x180
Retention:
Retained
IsDeepSleep:
No
Comment:
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name VALUE [7:0]
Bits 15 14 13 12 11 10 9 8
Name VALUE [15:8]
Bits 23 22 21 20 19 18 17 16
Name VALUE [23:16]
Bits 31 30 29 28 27 26 25 24
Name VALUE [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
0:31 VALUE RW R 0 Refer ARMv7M architecture spec and CM4 TRM
documents. See links in CM4_SCS.ACTLR register.
390
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers