Infineon TRAVEO T2G - 3.8.3.18 CM0 P_SCS_SHCSR

Technical Reference Manual 002-29852 Rev. *B
3.8.3.18 CM0P_SCS_SHCSR
Description:
System Handler Control and State Register
Address:
0xE000ED24
Offset:
0xD24
Retention:
Retained
IsDeepSleep:
No
Comment:
Controls and provides the status of system handlers.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:0]
Bits 15 14 13 12 11 10 9 8
Name SVCALLPEN
DED [15:15]
None [14:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits Name SW HW Default or
Enum
Description
15 SVCALLPENDED RW RW 0 0 SVCall is not pending.
1 SVCall is pending.
This bit reflects the pending state on a read, and
updates the pending state, to the value written, on a
write. (Pending state bits are set to 1 when an
exception occurs, and are cleared to 0 when an
exception becomes active.)
179
2022-04-18
TRAVEO™ T2G Automotive MCU: TVII-B-E-4M body controller entry registers