Infineon TRAVEO T2G - 23.9.34 SCB_INTR_SPI_EC

Technical Reference Manual 002-29852 Rev. *B
23.9.34 SCB_INTR_SPI_EC
Description:
Externally clocked SPI interrupt request
Address:
0x40600EC0
Offset:
0xEC0
Retention:
Retained
IsDeepSleep:
No
Comment:
The fields in this register are set by HW and are cleared by software by writing a '1'. These
interrupt causes are generated by externally clocked logic. HW clears the interrupt causes to
'0', when the IP is disabled.
Default:
0x0
Bit-field Table
Bits 7 6 5 4 3 2 1 0
Name None [7:4] EZ_READ
_STOP
[3:3]
EZ_WRITE
_STOP
[2:2]
EZ_STOP
[1:1]
WAKE_UP
[0:0]
Bits 15 14 13 12 11 10 9 8
Name None [15:8]
Bits 23 22 21 20 19 18 17 16
Name None [23:16]
Bits 31 30 29 28 27 26 25 24
Name None [31:24]
Bit-fields
Bits
Name SW HW Default or
Enum
Description
0 WAKE_UP RW1C A 0 Wake up request. Active on incoming slave request
when externally clocked selection is '1'.
Only used when CTRL.EC_AM_MODE is '1'.
1 EZ_STOP RW1C A 0 STOP detection. Activated on the end of a every
transfer (SPI deselection).
Only available in EZ and CMD_RESP mode and when
CTRL.EC_OP_MODE is '1'.
2 EZ_WRITE_STOP RW1C A 0 STOP detection after a write transfer occurred.
Activated on the end of a write transfer (SPI
deselection). This event is an indication that a buffer
memory location has been written to. For EZ mode: a
transfer that only writes the base address does NOT
activate this event.
Only used in EZ and CMD_RESP modes and when
CTRL.EC_OP_MODE is '1'.
3 EZ_READ_STOP RW1C A 0 STOP detection after a read transfer occurred.
Activated on the end of a read transfer (SPI
deselection). This event is an indication that a buffer
memory location has been read from.
Only used in EZ and CMD_RESP modes and when
CTRL.EC_OP_MODE is '1'.
1432
2022-04-18
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